With increasing levels of circuit, circuit board, and system integration, power consumption and heat dissipation are problems of growing concern at all three integration levels. Heat generated from power consumption that is not sufficiently dissipated or removed from a system enclosure increases circuit element temperature and degrades circuit performance and reliability. Therefore, reducing power consumption and integrated circuit operation temperature is of significant importance.
To date, reduction of integrated circuit temperature is accomplished in two ways: lowering the power consumption, and improving heat dissipation to the ambient environment. The first method is the preferred approach. A lowering of the power consumption is usually accomplished by scaling down the power supply voltage. The power supply voltage of integrated circuits has decreased from 5.0 volts several years ago to approximately 1.2 volts. However, further lowering of a power supply voltage will negatively impact the performance of the device. Because of the non-scalability of the built-in voltage of a silicon junction, there is little room for further reduction of the power supply voltage below about 1.2 volts if traditional semiconductor technology is used. Thus, for high performance very large scale integration (VLSI) and ultra large scale integration (ULSI) circuits, further lowering of the power supply voltage is not expected to be an effective approach.
In complimentary metal-oxide semiconductor (CMOS) synchronous digital systems, power consumption is a direct function of clock frequency. Accordingly, one way to conserve power in a digital system implemented with CMOS integrated circuits is to reduce the clock frequency. Thus, if system activity is determined to be below full capacity, the system clock can be controllably reduced to optimally reduce power consumption in the digital system.
A phase-locked loop (PLL) is a feedback-based control system that generates an output signal having a frequency that, through the feedback control, is urged into a fixed frequency relationship with an input reference signal. PLLs are used in frequency synthesizers, data transmission and recovery devices, and other applications where a stable clock signal is desired. As illustrated in FIG. 1, a conventional PLL 10 includes a phase-frequency detector (PFD) 12, a loop filter 14, a voltage-controlled oscillator (VCO) 16, and feedback divider 18. The PLL 10 outputs a signal that is generated by VCO 16 and has a frequency Fout. The feedback divider 18 receives and divides the frequency of Fout and provides the resulting divided-frequency (clock) signal (DIVCLK) to PFD 12, which also receives a reference clock signal (REFCLK). In response to the reference clock signal and the divided-frequency signal, the PFD 12 provides an UP signal or a DOWN signal to loop filter 14 depending on the relationship between the REFCLK and DIVCLK signals. In response to the UP and DOWN signals, loop filter 14 provides an analog voltage signal (V_CNTRL) that controls VCO 16. The output signal frequency Fout is proportional to the analog voltage signal. Frequency lock is achieved when the respective frequencies of the DIVCLK and REFCLK signals are identical.
PLLs, such as that shown in FIG. 1, are well-known. PLLs having switchable operating characteristics are also known. For example, spread-spectrum PLLs are known that have an adjustable output clock. However, the variation in the output clock is periodic and the output frequency range is rather limited to be useful for network routers and switches.